1. Field of the Invention
The present invention relates generally to a method of fabricating a diode for protecting a gate electrode of a field effect transistor and particularly to a method of fabricating a diode for protecting a gate electrode of a metal oxide semiconductor (MOS) transistor produced using MOS transistor production technology.
2. Description of the Background Art
Recent semiconductor device fabrication processes include a large number of steps using a plasma. For example, etching, depositing an interlayer insulation film, and the like exclusively use a plasma to do so.
It is known that in such steps using a plasma a phenomenon referred to as an xe2x80x9cantenna effectxe2x80x9d is caused if an element (for example, an interconnection) involved in the step has previously been connected to a gate electrode of a field effect transistor. The antenna effect is a phenomenon that a large difference in potential is introduced between a gate electrode and a semiconductor transistor that are positioned with a gate insulation film posed therebetween.
The antenna effect can significantly affect a function of a field effect transistor. More specifically, if a difference in potential no less than prescribed is introduced between the gate electrode and the semiconductor substrate the gate insulation film""s characteristics are impaired. If a further larger difference in potential is introduced and has reached a difference in potential that is no less than the gate insulation film""s breakdown voltage, the gate insulation film would have an electrical breakdown. The degradation of characteristics of a gate insulation film and the breakdown thereof that are caused by a step using a plasma are generally referred to as a xe2x80x9cplasma damagexe2x80x9d and need to be addressed as a factor impairing a function as a semiconductor device.
For example, with reference to FIG. 10, an aluminum interconnection M2 is formed by reactive-ion etching, an etching step using a plasma. This etching step introduces an electric charge in aluminum interconnection M2. This electric charge changes a node potential through an aluminum interconnection M1 and a gate pattern D1 and introduces a large difference in potential between a gate electrode and a semiconductor substrate.
One approach to address the plasma damage is to connect a protection diode to the gate electrode. In this approach, as shown in an equivalent circuit as shown in FIG. 11, a protection diode 31 has an anode (A) connected to a gate electrode (G) of a MOS transistor 30 and a cathode (K) to a ground potential. Used as this diode is for example a diode having a Zener breakdown for differences in potential smaller than that for which the gate insulation film suffers the plasma damage.
The diode passing an electric current in a reverse direction for a difference in potential smaller than that for which the gate insulation film suffers the plasma damage that is connected as shown, releases an electric charge to the ground potential when a large difference in potential is introduced between the gate electrode and the semiconductor substrate. The gate insulation film can thus avoid the plasma damage.
The aforementioned protection diode is typically fabricated into a semiconductor device in which a field effect transistor is formed. The protection diode is by providing a main surface of the semiconductor substrate with a doped region different in conductivity than the semiconductor substrate and using the doped region and a substrate region to provide a pn junction. The diode""s doped region thus provided is electrically connected to the gate electrode of the field effect transistor and the substrate region is electrically connected to a ground potential to allow the diode to function as a gate electrode protection diode.
One such protection diode thus configured is disclosed for example in Japanese Patent Laying-Open No. 1-168064. The protection diode disclosed in the publication has a doped region having its entire periphery surrounded by a gate pattern.
Preferably the protection diode is formed and connected to the gate electrode in a semiconductor device fabrication process at as early a step as possible so that in a subsequent step the plasma damage can be prevented and increased yields can be expected.
To form the protection diode, as described above, the diode""s junction needs to be reduced in area so that parasitic capacitance can be reduced and the protection diode can thus operate rapidly and response performance can be improved.
Minimizing in area the junction of the protection diode formed by providing a doped region in a main surface of a semiconductor substrate, as described above, entails reducing in size the doped region in the semiconductor substrate, as seen in a plane. Since the doped region is determined in size by a limit of resolution of photolithography, it can hardly be minimized to be smaller in size than the limit. For example, the protection diode disclosed in the aforementioned publication has a doped region which can only be minimized in size to the limit of resolution of photolithography, defined by a gate pattern.
An object of the present invention is to provide a method of fabricating a protection diode of a field effect transistor that can form a doped region as a constituent of the diode in a size smaller than a limit of resolution of photolithography.
The present method provides a protection diode formed by a doped region electrically connected to a gate electrode of a field effect transistor, and a substrate region located adjacent to the doped region and electrically connected to a ground potential. To achieve the above object the present method includes the steps of:
forming first and second conductive layers on a main surface of the semiconductor substrate, the first and second conductive layers being spaced from each other;
forming first and second sidewall films adjacent to a sidewall of the first conductive layer opposite the second conductive layer and a sidewall of the second conductive layer opposite the first conductive layer, respectively; and
with the first and second conductive layers and the first and second sidewall films used as a mask, implanting a dopant in the semiconductor substrate to form the doped region.
With the above process used to form a doped region, a sidewall film arranged adjacent to a sidewall of a conductive layer can serve as a mask when a dopant is implanted, and the doped region can be formed to have a size smaller than a limit of resolution of photolithography. This allows the protection diode""s pn junction interface to be significantly smaller in area than conventional to reduce the diode""s parasitic capacitance and provide enhanced response performance. Fabricating the protection diode in a semiconductor device fabrication process at as early a stage as possible and connecting the diode to a gate electrode of a field effect transistor, can prevent plasma damage in subsequent process steps and thus be expected to contribute to increased yields. Note that the first and second conductive layers can be either separate conductive layers formed independently or portions of a single conductive layer.
Preferably the present method further includes the step of forming a plurality of element isolating regions in a main surface of the semiconductor substrate to traverse the first and second conductive layers when the semiconductor substrate is seen in a plane, wherein the step of implanting includes using the first and second sidewall films and the element isolating region as a mask.
In the present method the step of forming the first and second conductive layers includes forming a conductive layer having an opening when the semiconductor substrate is seen in a plane and the step of forming the first and second sidewall films includes forming a sidewall film adjacent to a sidewall of the opening.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.